Alcatel-Lucent Specialist, 5G ASIC Physical Design in Espoo, Finland
Nokia is a global leader in the technologies that connect people and things. With state-of-the-art software, hardware and services for any type of network, Nokia is uniquely positioned to help communication service providers, governments, and large enterprises deliver on the promise of 5G, the Cloud and the Internet of Things.
Serving customers in over 100 countries, our research scientists and engineers continue to invent and accelerate new technologies that will increasingly transform the way people and things communicate and connect.
Nokia Mobile Networks (MN) is responsible for managing Nokia s infrastructure assets and making select investments in advanced research and development to drive innovation for 5G applications. The Architectures, Technologies, and R&D Foundation (ATF) division within Mobile Networks creates valuable IP for Nokia by engaging with leading business-to-business (B2B) customers to enhance their competitive advantage.
ATF s 5G DFE & RFIC program, located in Sunnyvale, California, innovates and develops differentiating wireless infrastructure solutions for Nokia s 5G products. The team is multi-disciplinary and enjoys fruitful collaborative partnerships with top universities, international research institutes and network operators. Be part of this exciting team and successfully drive the future of wireless communications!
We are now looking for Specialist, 5G ASIC Physical Design to join our team.
*Key responsibilities *
In this role, you will be responsible for back-end ASIC design including physical place and route, timing analysis and fixing, and physical verification. You will work with IC design teams to successfully tape out next generation low power DFE ASICs.
5-8 years of industry experience in digital ASIC physical design implementation (placement, CTS, routing, STA, LVS/DRC,) in advance technologies.
Experience with Synopsys and Cadence ASIC tool-set.
Experience with high-frequency designs.
Familiar with STA tool and timing closure methodologies.
Experience in timing closure of DDR3/4 interface, power-grid, clock-tree, and IR drop analysis.
Proficiency in scripting languages such as Tcl, or Perl
Experience in 28nm technology node.
Mixed signal experience is a distinct advantage.
Experience with interfacing with Mixed-Signal / Analog IC teams a distinct advantage.
MS in Electrical Engineering (or related discipline) desired.
Job: fNokia System on Chip Development
Primary Location: Europe North-Finland-Finland-Espoo
Req ID: 1700000DK0